1. Field of the Invention
The present invention relates to semiconductor circuit devices and, more specifically to a semiconductor circuit device having a hierarchical power supply structure.
2. Description of the Background Art
In a recent semiconductor memory, a threshold value of a transistor is becoming lower with decrease in an operating power supply voltage. To prevent an increase in subthreshold leakage current which is caused by the decrease in the threshold value of the transistor, various SCRC (Subthreshold Current Reduced Control) techniques are developed (see for example Japanese Patent Laying-Open No. 6-237164).
An internal control of a DRAM (Dynamic Random Access Memory) is divided into two types of operations, that is, row and column related operations. With recent tendency toward multiply banks and an independent operation for every bank, a structure of a circuit for controlling a bank is becoming more complicated. In addition, the number of circuits in a whole chip increases, thereby resulting in an increase in leakage current during stand-by.
According to the above described SCRC technique, a hierarchical power supply structure has been proposed to reduce subthreshold leakage current during such stand-by. In the hierarchical power supply structure, sub power supply and ground lines are provided in addition to main power supply and ground lines, a logic circuit such as a CMOS (Complementary Metal Oxide Semiconductor) inverter circuit outputting a signal at an H (logic high) level during stand-by is connected between the main and sub power supply lines, and a logic circuit such as a CMOS inverter circuit outputting a signal at an L (logic low) level is connected between the sub power supply line and the main ground line, so that the sub power supply and ground lines are electrically disconnected from the main power supply and ground lines during stand-by, respectively.
In such hierarchical power supply structure, a source of a P channel MOS transistor in the CMOS inverter circuit outputting the signal at the H level is connected to the main power supply line, whereas a source of an N channel MOS transistor is connected to the sub ground line. Thus, a source potential of the N channel MOS transistor is higher than a ground potential during stand-by, so that subthreshold leakage current for the N channel MOS transistor is reduced. On the other hand, a source of an N channel MOS transistor in the CMOS inverter circuit outputting the signal at the L level is connected to the main ground line, whereas a source of a P channel MOS transistor is connected to the sub power supply line. Thus, a source potential of the P channel MOS transistor is lower than a power supply potential during stand-by, so that subthreshold leakage current for the P channel MOS transistor is reduced.
Although the above described hierarchical power supply structure can be employed for a logic circuit in which a logic level of an output signal during stand-by is determined, it cannot be employed for that in which the logic level is not determined. Thus, such logic circuit has to be connected between the main power supply and ground lines, whereby subthreshold leakage current cannot be reduced during stand-by.
In a latch circuit, particularly, reduction in subthreshold leakage current cannot be achieved by the above described hierarchical power supply structure as a logic level of a signal to be latched is not determined during stand-by.